This application claims priority to Italian Application Serial Number 2002A000821, filed Sep. 20, 2002.
1. Field of the Invention
The present invention relates to charge pump circuits. More particularly, the present invention relates to a negative charge pump that switch the bulk of each transistor stage to the lowest potential node to minimize body effect.
2. The State of the Art
In integrated circuit applications such as flash memory, EEPROMs and the like, generation of a negative voltage is required. In the case of non-volatile memories that operate with only one level of supply voltage, the internal high voltages are generated with charge pumps. The charge pumps are used to generate both positive and negative voltages. Charge pumps for generating negative voltages are usually formed using triple-well processes. Such negative charge pumps use n-channel MOS transistors pump a voltage line to a negative value.
Referring to FIG. 1, a schematic diagram depicts a commonly employed prior-art implementation of a negative charge pump formed from n-channel MOS transistors. Charge pump 10 includes three stages, 12, 14, and 16, driven by a four-phase clock. Each stage includes two n-channel MOS transistors and two capacitors.
Stage 12 includes n-channel MOS transistors 18 and 20. N-channel MOS transistor 18 has its drain coupled to ground, its source coupled to the source of n-channel MOS transistor 20 and its gate coupled to the drain of n-channel MOS transistor 20 and to the phase-D signal of the clock through capacitor 22. The gate of n-channel transistor 20 is coupled to the drain of n-channel MOS transistor 18 and to the phase-A signal of the clock through capacitor 24.
Stage 14 includes n-channel MOS transistors 26 and 28. N-channel MOS transistor 26 has its drain coupled to the sources of n-channel MOS transistors 18 and 20 from stage 12, its source coupled to the source of n-channel MOS transistor 28 and its gate coupled to the drain of n-channel MOS transistor 28 and to the phase-B signal of the clock through capacitor 30. The gate of n-channel transistor 28 is coupled to the drain of n-channel MOS transistor 26 and to the phase-C signal of the clock through capacitor 32.
Stage 16 includes n-channel MOS transistors 34 and 36. N-channel MOS transistor 34 has its drain coupled to the sources of n-channel MOS transistors 26 and 28 from stage 14, its source coupled to the source of n-channel MOS transistor 36 and its gate coupled to the drain of n-channel MOS transistor 36 and to the phase-D signal of the clock through capacitor 38. The gate of n-channel transistor 36 is coupled to the drain of n-channel MOS transistor 34 and to the phase-A signal of the clock through capacitor 40.
As may be seen from an examination of FIG. 1, each of the n-channel MOS transistors 18, 20, 26, 28, 34, and 36 has its bulk connected to the most negative node (VNEG at reference numeral 42) that serves as the output of the charge pump. The reason for this is to avoid turning on the parasitic bipolar transistor formed in each stage by the buried n-well, the p-well and the n+ source and drain regions of the n-channel MOS transistors.
In the charge-pump circuit of FIG. 1, the parasitic bipolar transistor in the last stage 16 can be turned on during the transition toward the steady state (from 0 to VNEG) when the phase-A signal of the clock goes low to sink current from the load. If the bipolar transistor turns on, the efficiency of the charge pump is compromised because the current is no longer sunk by the load but from the grounded buried-n-well collector of the bipolar transistor.
Moreover another drawback of the implementation of FIG. 1 is that body effect of the n-channel MOS transistors of the charge pump increases moving from right to left of the pump. This can severely limit the performance of the charge pump in terms of maximum negative voltage in those applications where very low power supply voltages are employed.
Referring now to FIG. 2, a schematic diagram shows a prior-art solution that can be adopted to reduce but does not eliminate the body effect inside each stage of the charge pump. The circuit of FIG. 2 is substantially similar to the circuit of FIG. 1, except that the bulks of the two n-channel MOS transistors in each stage are coupled to the output node of the stage. Thus, the bulks of n-channel MOS transistors 18 and 20 are coupled to their common sources; the bulks of n-channel MOS transistors 26 and 28 are coupled to their common sources; and the bulks of n-channel MOS transistors 34 and 36 are coupled to their common sources. This configuration does not solve the parasitic bipolar turn-on problem in the last stage 16.
Another technique to reduce the body effect is disclosed in U.S. Pat. No. 6,130,572. This circuit has the same drawback of FIG. 2. In particular, for low-voltage applications, the problem of threshold-voltage increase due to body effect is very important because the difference between the VDD and Vth of the MOS transistors is reduced and degrades performance.
Another prior-art technique used to reduce the influence of the body effect is to use a level shifter to boost the phase of the charge pumps but in this way the efficiency (Iload/IVDD) of the charge pump is reduced. Another drawback of this method is that the silicon area is undesirably increased.
The present invention provides a n-channel MOS transistor charge pump in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.
A negative-voltage charge pump has a plurality of operating phases and comprises a plurality of stages, each stage comprising at least two n-channel MOS transistors each including bulk regions. Each of said stages also includes a parasitic bipolar transistor. The bulk regions are switchably coupled during each of the operating phases to a circuit node having a potential such that the parasitic bipolar transistor will not turn on.